1. Field of the Invention
The present invention relates to a reproduced signal waveform processing apparatus. More specifically, the present invention relates to a reproduced signal waveform processing apparatus for extracting a reproduced digital data by equalizing a waveform of a signal reproduced from a recording medium such as a magnetic medium or the like.
2. Description of Related Art
In a conventional magnetic recording-reproducing apparatus for recording and reproducing digital data, a reproduced signal is equalized, and then, discriminated in a Viterbi decoder or the like for data extraction.
According to such a conventional system, it is required that the sampling of decoding is performed in precise synchronization with the reproduced data, and that the reproduced data is subjected to waveform equalization so as to be easily discriminated.
FIG. 7 is a block diagram showing a conventional reproduced signal waveform processing apparatus used in a magnetic recording-reproducing apparatus, and which mainly consists of: an amplifier 101 for amplifying a reproduced signal 100; an equalizer 102 for equalizing reproduced signal amplified in the amplifier 101; an A/D converter (ADC) for converting a signal equalized in the equalizer 102 into a digital signal of reproduced data 107; a Viterbi decoder 104 for Viterbi-decoding the reproduced data 107 converted in the A/D converter 103; and a phase locked loop (PLL) circuit 105 for performing phase locked looping of a signal equalized in the equalizer 102. Among them, the equalizer 102, the A/D converter (ADC) 103 and the PLL 105 constitute a reproduced signal waveform processing unit 106.
In this arrangement described above, the reproduced signal 100 reproduced by a head is amplified in the amplifier 101, and the waveform thereof is equalized by the equalizer 102. The reproduced data 107 is discriminated in the Viterbi decoder 104. The PLL 105 produces a reproducing clock signal 108 from the reproduced signal that is subjected to waveform equalization in the equalizer 102, and supplies it to the A/D converter 103 and the Viterbi decoder 104. The A/D converter 103 extracts discrete reproduced data 107 by sampling the reproduced signal after the equalization with the reproducing clock signal 108.
Further, the reproducing clock signal 108 is used as a synchronization signal for the Viterbi decoder 104 and subsequent stages in the system. The Viterbi decoder 104 decodes the reproduced data 107 by the maximum likelihood decoding, discriminates digital information magnetically recorded, and outputs it as data 109.
Here, the reproduced signal waveform processing unit 106 is a unit for equalizing the waveform of the reproduced signal 100, and for obtaining a reproduced data 107 which is separated and equalized by subjecting it to the clock extraction and sampling.
In the example shown in FIG. 7, the equalizer 102 for equalizing the reproduced signal and the PLL 105 for extracting the reproducing clock are constituted with analog circuits. However, in order to achieve various objects such as a high precision equalization and clock extraction, elimination of adjustments, a large-scale integration on an LSI chip, a reduced power consumption by integrating the chip with a signal processing IC as well as a reduced cost of manufacture, these equalizer and PLL are desired to be digitalized.
In FIG. 8, there is shown an example, in which its equalizer is digitalized, of a reproduced signal waveform processing unit for use in a magnetic recording-reproducing apparatus system.
In FIG. 7 and FIG. 8, like functions are designated by like reference numerals, and only features which have not been previously described with FIG. 7 will be described below.
An A/D converter (ADC) extracts a discrete reproduced data 107 by sampling the reproduced signal 100 which is amplified in a signal amplifier 101 with a reproducing clock signal 108 which is generated by a voltage controlled oscillator (VCO) 203.
An equalizer 201 equalizes a digital signal digitalized in the A/D converter 103 and outputs it as the reproduced data 107. A phase frequency controller 202 detects phase and frequency error information from the reproduced data 107 after the equalization by executing digital processing, and controls an oscillation frequency of the voltage controlled oscillator (VCO) 203 in accordance with a result of the detection. The voltage controlled oscillator (VCO) 203 varies its oscillation frequency in response to an output of the phase frequency controller 202 so as to obtain the reproducing clock signal 108. The reproducing signal 108 is used as a synchronizing signal not only in the A/D converter 103 but also in the equalizer 201, the Viterbi decoder 104, the phase frequency controller 202 and subsequent stages in the system. Here, a feedback loop including the A/D converter 103, the equalizer 201, the phase frequency controller 202 and the voltage controlled oscillator (VCO) 203 corresponds to the analog PLL 105 shown in FIG. 7, and its reproducing clock signal 108 is enabled to be oscillated in precise synchronization with the reproduced signal 100.
It should be noted that in the digital type of reproduced waveform processing unit 106 shown in FIG. 8, an equalizing characteristic in the equalizer 201 has a critical effect on an error rate of data to be extracted. Therefore, it is required for the digital type of equalizer 201 to be able to precisely equalize an equalization error contained in the reproduced signal 100.
On the other hand, in the case where the equalizer 201 in the digital type waveform processing unit is realized by utilizing a digital system, some delay may occur per unit clock. This delay becomes a dead time element in the PLL, reducing a phase margin in its control system, thereby restraining a loop gain in the PLL. That is, when its gain is set at an higher value in order to realize a fast pull-in, there may be a problem such that, in a system having a large dead time element in the feedback control of the PLL, the phase margin is substantially reduced and causes instability in the system.
Here, we consider an application of the reproduced waveform processing unit described above to a magnetic recording-reproducing apparatus system, which utilizes a helical scan recording/reproducing of information on and from, for example, a magnetic tape. The equalization characteristics required for the equalizer 201 shown in FIG. 8 are, for example, an LPF characteristic for DC cut-off, an inverse characteristic to electromagnetic conversion, and a Nyquist filtering characteristic.
An equalizer that may realize these characteristics described above may be realized by using an IIR (Infinite Impulse Response) filter for reducing a low frequency region, achieving an integrating equalization, a high frequency region enhancement and attenuating a Nyquist frequency region. However, in order to be able to strictly satisfy these filter characteristics matching with target characteristics, the system becomes more complicated, and due to an increased amount of digital processing involved, dead time elements may increase. Further, for the helical scan type magnetic recording-reproducing apparatus, it is even required to equalize variations and fluctuations of products, which are inherent in constituting elements such as a tape, a magnetic recording/reproducing head, a rotary transformer that cannot be avoided in the manufacture thereof. For the equalizer in the arrangement described above, although a degree of freedom or system flexibility is increased because of an increased number of parameters, it becomes very difficult to perform a parameter setting for optimal equalization thereof.
Alternatively, we consider a case in which the equalizer 201 in FIG. 8 includes a transversal filter. In this case, with regard to the equalization of frequency characteristics, it is possible to provide measures for fluctuations in manufacturing of constituent elements by employing adaptive equalization using an automatic equalization method such as an LMS (Least Mean Square) algorithm.
An example of the conventional apparatus described above is disclosed in Japan Patent Application Laid-Open Publication No. H07-302467, pp. 3-4 and FIG. 1.